Synopsys Design Compiler Tutorial 2021 ⇒ «TOP»

set_optimize_registers true -design my_design compile_ultra -retime Use code with caution. High-Fanout Net Synthesis

: Specifies the standard cell library ( .db format) provided by your foundry. The tool selects physical cells from this library to build your gate-level netlist.

# Model driving strength of inputs using an existing library cell inverter set_driving_cell -lib_cell INVX4 [remove_from_collection [all_inputs] [get_ports clk]] # Model external capacitive loading on output pins set_load 0.05 [all_outputs] Use code with caution. Operating Conditions and Area Constraints synopsys design compiler tutorial 2021

# Report area characteristics report_area -hierarchy > ../output/reports/area.rpt # Report timing summaries (focusing on worst slack paths) report_timing -delay max -max_paths 10 > ../output/reports/timing_setup.rpt report_timing -delay min -max_paths 10 > ../output/reports/timing_hold.rpt # Report power consumption estimates report_power -hierarchy > ../output/reports/power.rpt # Report DRC (Design Rule Constraints) violations like max capacitance or transition times report_constraint -all_violators > ../output/reports/constraints.rpt Use code with caution. Step 5: Exporting the Synthesized Database

If your timing and area metrics look acceptable, save your gate-level netlist and design data to pass on to the Place and Route (P&R) tools. # Model driving strength of inputs using an

# In your .bashrc or .cshrc setenv SYNOPSYS_HOME /tools/synopsys/2021.03 setenv PATH $SYNOPSYS_HOME/bin:$PATH setenv SNPSLMD_LICENSE_FILE 27000@license_server setenv LM_LICENSE_FILE 27000@license_server

Once constraints are applied, you can invoke the optimization engine using the compile or compile_ultra commands. # In your

Before launching Design Compiler, you must organize your workspace and define your target technology libraries. Create a clean project directory with the following structure: